IBM's nanostack chip aims to keep Moore's Law alive a decade

The News

IBM has done what chipmakers long insisted was nearly impossible: it has kept the shrinking going by building upward. The company on 25 June unveiled a prototype it calls "nanostack", a chip that crams roughly 100 billion transistors onto a slice of silicon the size of a fingernail. That is twice the transistor density of the most advanced design IBM showed in 2021.

The trick is vertical stacking. Rather than squeezing devices closer together on a flat plane, IBM's researchers piled them atop one another using a complementary field-effect transistor, or CFET, layout. The nanosheets at the heart of the design are about 15 atoms thick, separated by gaps of 9 nanometres, and the architecture carries a 0.7-nanometre node label. IBM says the result does 50% more work in the same window of time while drawing 70% less energy.

The work was not done alone. IBM credits collaboration with Intel, Samsung, TSMC and the Belgian research hub Imec. "It's a meaningful leap forward," said Jay Gambetta, director of IBM Research. "This puts another ten, fifteen years on the roadmap," added Dan Hutcheson, vice chair at TechInsights, referring to the slow death sentence long hanging over Moore's Law.

Why It Matters

For more than half a century, the industry doubled transistor counts by making each device smaller, an approach now hitting the brick wall of atomic physics. The last comparable turning point was the arrival of FinFET transistors around 2011, when Intel rebuilt the transistor in three dimensions at its 22-nanometre node to keep scaling alive. Stacking is the next such reinvention, which is why so many rival firms have lined up behind it.

The payoff is efficiency as much as speed. Data centres training large models are now constrained less by chip supply than by power and cooling. A part that performs better while consuming far less electricity is exactly what operators building model infrastructure have been demanding. IBM expects widespread deployment within a decade, with manufacturing partners doing the heavy lifting.

Indian Angle

India watches this from a particular vantage point. The country's INR 76,000 crore Semiconductor Mission, launched in 2021, has so far drawn fabrication plants aimed squarely at mature nodes. The Tata Electronics and Powerchip facility coming up in Dholera, Gujarat, and Micron's assembly and test site at Sanand are not chasing 0.7-nanometre geometries; they target 28-nanometre-and-above chips and packaging. A leading-edge breakthrough like this sits several technology generations from anything Indian fabs will produce this decade.

That is not as discouraging as it sounds. CFET and 3D stacking shift value toward advanced packaging, assembly and test, precisely the segment where India planted its flag first. As transistors go vertical, the work of bonding, testing and integrating those stacks grows more valuable, and that is the part of the chain India is building. Indian chip-design startups such as Mindgrove Technologies, which design rather than fabricate, also gain from a roadmap that keeps cutting-edge silicon improving and affordable.

IBM runs one of its largest research operations outside the United States in Bengaluru, and Indian engineers are scattered across the supply chain that produced this result. The breakthrough is a reminder that India's near-term realism on fabs need not mean absence from the frontier of design and packaging.

FAQ

When could nanostack chips reach the market?

IBM expects widespread deployment in data centres within roughly a decade, working through manufacturing partners. The 25 June unveiling was a research prototype, not a shipping product, so commercial parts built on the 0.7-nanometre design remain several years out even on an optimistic timeline.

How is this different from simply making transistors smaller?

Conventional progress shrank each transistor on a flat surface until atomic limits intervened. IBM's CFET approach instead stacks devices vertically, raising density without further shrinking. It echoes the 2011 shift to three-dimensional FinFET transistors, the last architecture change that meaningfully extended Moore's Law.

Does this help India's semiconductor ambitions?

Indirectly. India's fabs target mature 28-nanometre-and-above nodes, not 0.7-nanometre frontier chips. But vertical stacking raises the value of advanced packaging, assembly and test, the segment India is building first, and keeps design tools used by Indian startups improving.

Where can I read the original report?

The full announcement and technical detail were reported by MIT Technology Review, linked below.

This story was reported by MIT Technology Review. Read the full original coverage at MIT Technology Review.